GS8342D08/09/18/36BD-400/350/333/300/250 36Mb SigmaQuad-II™ Burst of 4 SRAM
2022-03-23
■SigmaQuad-II™ Family Overview
●The GS8342D08/09/18/36BD are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342D08/09/18/36BDSigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
■Features
●Simultaneous Read and Write SigmaQuad™ Interface
●JEDEC-standard pinout and package
●Dual Double Data Rate interface
●Byte Write controls sampled at data-in time
●Burst of 4 Read and Write
●1.8 V +100/–100 mV core power supply
●1.5 V or 1.8 V HSTL Interface
●Pipelined read operation
●Fully coherent read and write pipelines
●ZQ pin for programmable output drive strength
●IEEE 1149.1 JTAG-compliant Boundary Scan
●Pin-compatible with present 144 Mb devices
●165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
●RoHS-compliant 165-bump BGA package available
●The GS8342D08/09/18/36BD are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342D08/09/18/36BDSigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
■Features
●Simultaneous Read and Write SigmaQuad™ Interface
●JEDEC-standard pinout and package
●Dual Double Data Rate interface
●Byte Write controls sampled at data-in time
●Burst of 4 Read and Write
●1.8 V +100/–100 mV core power supply
●1.5 V or 1.8 V HSTL Interface
●Pipelined read operation
●Fully coherent read and write pipelines
●ZQ pin for programmable output drive strength
●IEEE 1149.1 JTAG-compliant Boundary Scan
●Pin-compatible with present 144 Mb devices
●165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
●RoHS-compliant 165-bump BGA package available
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