Designers Love Us. Packets Fear Us. SigmaQuad-II™ and SigmaDDR-II™SRAMs
■SigmaQuad SRAMs are synchronous memories with separate read and write data buses. “Quad” refers to their ability to transfer 4 beats of data (2 beats per data bus) in a single clock cycle.
●SigmaDDR™ SRAMs
■SigmaDDR SRAMs are synchronous memories with a common read and write data bus. “DDR” refers to their ability to transfer 2 beats of data on the data bus in a single clock cycle. GSI’s SigmaQuad and SigmaDDR devices are compatible with all competitor Quad Data Rate and Double Data Rate SRAMs, respectively.
●Features
■1.1G memory transactions per second (SigmaQuad-II+™)
■Extensive range of design options—Quad & Double Data Rates, 1.5–2.5 cycle Read Latencies, 2- and 4-word data bursts
■User-configurable signal termination and output drive settings
■Densities for every performance point—18Mbit up to 288Mbit
■Constructed using foundry-standard CMOS and 165-bump BGA packaging (both leaded and RoHS-compliant options)
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GS8182S 、 GS8342S 、 GS8662S 、 GS81302S 、 GS82582S 、 GS8182R 、 GS8342R 、 GS8662R 、 GS81302R 、 GS82582R 、 GS8182T 、 GS8342T 、 GS8672T 、 GS8662T 、 GS81302T 、 GS82582T 、 GS8182D 、 GS8342D 、 GS8662D 、 GS8672D 、 GS81302D 、 GS82582D 、 GS8182Q 、 GS8342Q 、 GS8662Q 、 GS8672Q 、 GS81302Q 、 GS82582Q |
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Supplier and Product Introduction |
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Please see the document for details |
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BGA |
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English Chinese Chinese and English Japanese |
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2015/5/28 |
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1.1 MB |
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