LatticeECP3 sysCONFIG Usage Guide Technical Note
●Configuration is the process of loading or programming a design into volatile memory of an SRAM-based FPGA. This is accomplished via a bitstream file, representing the logical states, that is loaded into the FPGA internal configuration SRAM memory. The functional operation of the device after programming is determined by these internal configuration RAM settings. The SRAM cells must be loaded with configuration data each time the device powers up.
●The configuration memory in LatticeECP3™ FPGAs is built using volatile SRAM; therefore, an external non-volatile configuration memory is required to maintain the configuration data when the power is removed. This non-volatile memory supplies the configuration data to the LatticeECP3 when it powers up or anytime the device needs to be updated.
●To support multiple configuration options the LatticeECP3 supports the Lattice sysCONFIG™ interface as well as the dedicated JTAG port. The available configuration options, or modes, are listed in Table 1.1.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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September 2021 |
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Revision 3.3 |
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FPGA-TN-02192-3.3 |
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1.7 MB |
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