LatticeECP3 Slave SPI Port User Guide Technical Note
●Prior to the introduction of the Serial Peripheral Interface Bus (SPI), the standard methods for configuring an FPGA using a CPU were through the following ports or interfaces:
▲JTAG
▲SCM (Serial Configuration Mode)
▲PCM (Parallel Configuration Mode)
●Each port has advantages and disadvantages depending on the given application:
▲The JTAG port requires a custom driver, which can be challenging to integrate into the system software.
▲The SCM port does not support read back.
▲The PCM port requires usage of approximately 14 General Purpose Input/Output pins (GPIO). GPIOs are precious resources that may be needed for user I/O.
▲For most of the FPGA devices in the market place, read back is only supported with a PCM (CPU type) port.
●SPI is an industry standard interface that is available on most CPUs and serial Flash memory devices. The 32-bit CPU from Freescale™ Semiconductor shown in Figure 1.1illustrates the availability of the SPI interface. The drivers for reading and writing from SPI memory devices are readily available for modern digital systems.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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December 2019 |
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Revision 1.9 |
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FPGA-TN-02136-1.9 |
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1.3 MB |
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