Workaround for Lattice ECP5(LFE5UM) Known Issue with SerDes Interface Connections Due to Unstable Reset Soft Logic

PublishTime：2022-03-23

■Detailed Workaround Description：
●This workaround is organized on a single channel basis, contact your local Lattice representative for other use cases.
●Lattice developed a workaround procedure that implements ‘extended Reset Soft Logic = extRSL’ to bring-up the SerDes/PCS at a stable state. The workaround is to remove the current receiver reset signals from the current RSL and add a new module that will drive the receiver reset signals instead.
●The new source code contains the necessary functions for a detailed signal monitoring and controlled reset scenario. It isthe single point of control for all the receiver resets in the PCS portion of the design.The transmitter reset signals will still be driven by the original RSL.

Brand of Product：	Lattice
Part#：	LFE5UM 、 ECP5 、 ECP5-5G 、 LFE5UM-5G More Part#
Product Category：	FPGA More
Application：	More
Data Type：	Datasheet More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	June 2021
Version Number：
Data Encoding：	FPGA-PB-02001
Data Size：	1.5 MB

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