FIR Filter IP Core -Lattice Radiant Software User Guide
●The Lattice Finite Impulse Response(FIR) Filter IP Core is implemented using high performance sysDSP™ blocks available in Lattice devices. The input data, coefficient and output data widths are configurable over a wide range. The IP core uses full internal precision while allowing variable output precision with several choices for saturation and rounding. The coefficients of the filter can be specified at generation time and/or reloadable during run-time through input ports.
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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June 2021 |
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Revision 1.1 |
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FPGA-IPUG-02095-1.1 |
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1.1 MB |
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