GD9Fx1GxF2A DATASHEET
●GigaDevice GD9Fx1G8F2A and GD9Fx1G6F2A are 1Gbit with spare 64Mbit capacity. A program operation can be performed in typical tPROG on the 2176-byte page and an erase operation can be performed in typical tBERS on a 128K+8K-bytesblock. Data in the data page can be read out at tRC cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. GD9Fx1G8F2A and GD9Fx1G6F2A′s provide extended reliability of 100K program/erase cycles with ECC (Error Correcting Code).
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GD9Fx1GxF2A 、 GD9FU1G8F2AMG 、 GD9FU1G6F2AMG 、 GD9FU1G8F2ALG 、 GD9FU1G6F2ALG 、 GD9FU1G8F2ADG 、 GD9FU1G6F2ADG 、 GD9FS1G8F2AMG 、 GD9FS1G6F2AMG 、 GD9FS1G8F2ALG 、 GD9FS1G6F2ALG 、 GD9FS1G8F2ADG 、 GD9FS1G6F2ADG 、 GD9FU1G8F2AMGI |
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Datasheet |
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Please see the document for details |
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TSOP(I)-48;FBGA-63;FBGA-48;TSOPI-48 |
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English Chinese Chinese and English Japanese |
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2021-11-01 |
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Version 2.8 |
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3.7 MB |
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