GD9Fx1GxF2A
performed in typical tPROG on the 2176-byte page and an erase operation can be performed in typical tBERS on a 128K+8K-bytes block. Data in the data page can be read out at tRC cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. GD9Fx1G8F2A and
GD9Fx1G6F2A′s provide extended reliability of 100K program/erase cycles with ECC (Error Correcting Code).
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GD9Fx1GxF2A 、 GD9Fx1G8F2A 、 GD9Fx1G6F2A 、 GD9FU1G8F2AMG 、 GD9FU1G6F2AMG 、 GD9FU1G8F2ALG 、 GD9FU1G6F2ALG 、 GD9FU1G8F2ADG 、 GD9FU1G6F2ADG 、 GD9FS1G8F2AMG 、 GD9FS1G6F2AMG 、 GD9FS1G8F2ALG 、 GD9FS1G 、 GD9FS1G8F2ADG 、 GD9FS1G6F2ADG 、 GD9FS1G8F2A 、 GD9FS1G6F2A 、 GD9FU1G8F2A 、 GD9FU1G6F2A 、 GD9FU1G8F2AMGI 、 GD9FS1G6F2ALG 、 GD9Fx1G8F2AMG 、 GD9Fx1G6F2AMG |
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Datasheet |
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Halogen Free 、 Lead Free |
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Please see the document for details |
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Industrial |
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FBGA-63;FBGA-48;TSOP-48;TSOPI-48;BGA63;BGA48 |
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English Chinese Chinese and English Japanese |
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2019-5-15 |
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Version No 2.7 |
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3.4 MB |
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