GS8662D08/09/18/36BD-400/350/333/300/250 72Mb SigmaQuad-II™ Burst of 4 SRAM product specification
●The GS8662D08/09/18/36BD are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8662D08/09/18/36BD SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
■Features
●Simultaneous Read and Write SigmaQuad™ Interface
●JEDEC-standard pinout and package
●Dual Double Data Rate interface
●Byte Write controls sampled at data-in time
●Burst of 4 Read and Write
●1.8 V +100/–100 mV core power supply
●1.5 V or 1.8 V HSTL Interface
●Pipelined read operation
●Fully coherent read and write pipelines
●ZQ pin for programmable output drive strength
●IEEE 1149.1 JTAG-compliant Boundary Scan
●Pin-compatible with present 144 Mb devices
●165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
●RoHS-compliant 165-bump BGA package available
■Clocking and Addressing Schemes
●The GS8662D08/09/18/36BD SigmaQuad-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead.
●Each internal read and write operation in a SigmaQuad-II B4 RAM is four times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. Therefore the address field of a SigmaQuad-II B4 RAM is always two address pins less than the advertised index depth (e.g., the 8M x 8 has a 2M addressable index).
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GS8662D08BD-400 、 GS8662D08BD-333 、 GS8662D08BD-300 、 GS8662D08BD-350 、 GS8662D08BD-250 、 GS8662D09BD-400 、 GS8662D09BD-350 、 GS8662D09BD-333 、 GS8662D09BD-300 、 GS8662D09BD-250 、 GS8662D18BD-400 、 GS8662D18BD-350 、 GS8662D18BD-333 、 GS8662D18BD-300 、 GS8662D18BD-250 、 GS8662D36BD-400 、 GS8662D36BD-350 、 GS8662D36BD-333 、 GS8662D36BD-300 、 GS8662D36BD-250 |
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Datasheet |
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Please see the document for details |
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BGA |
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English Chinese Chinese and English Japanese |
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8/2017 |
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Rev: 1.02d |
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573 KB |
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