AS4C128M8D1-6TIN
DDR DRAM organized as 4 banks x 32Mbit x 8. The
AS4C128M8D1-6TIN achieves high speed data
transfer rates by employing a chip architecture that
pre-fetches multiple bits and then synchronizes
the output data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A
sequential and gapless data rate is possible
depending on burst length, CAS latency and speed
grade of the device.
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Datasheet |
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Halogen Free 、 JEDEC 、 Pb Free |
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Please see the document for details |
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Industrial |
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English Chinese Chinese and English Japanese |
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Dec. 2016 |
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Rev 1.0 |
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2.2 MB |
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