CORDIC IP Core -Lattice Radiant Software User Guide
■This user's guide provides a description of Lattice's Coordinate Rotation Digital Computer (CORDIC) IP core. The CORDIC IP Core is configurable and supports several functions,including rotation, translation, sin and cos, and arctan. Two architecture configurations are supported for the arithmetic unit: parallel, in which the output data is calculated in a single clock cycle, and word-serial, in which the output data is calculated over multiple clock cycles. The input and output data widths and computation iterative numbers are configurable over a wide range of values. The IP core uses full precision arithmetic internally while supporting variable output precision and several choices of rounding algorithms.
■This design is implemented in Verilog. It can be targeted to CrossLink™-NX and Certus™-NX FPGA devices and implemented using the Lattice Radiant® software Place and Route tool integrated with the Synplify Pro® synthesis tool.
●Features
■The key features of CORDIC IP Core include:
▲Functional configurations
◆Vector rotation (Polar to rectangular)
◆Vector translation (Rectangular to Polar)
◆Sin and Cos
◆Arctan
▲Input data widths from 8 to 32 bits
▲Iterative number from 4 to 32
▲Optional pre-rotation module
▲Optional amplitude compensation scaling module to compensate for CORDIC algorithm's output amplitude scale factor
▲Selectable rounding : Truncation, Rounding Up, Rounding away from zero, Convergent Rounding
▲Parallel architectural configuration for high throughput
▲Word serial architectural configuration for small area
▲Signed 2's complement data
▲Optional control signals: ce_i and sr_i
▲Full precision arithmetic
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CORDIC-CNX-U 、 CORDIC-CNX-UT 、 CORDIC-CTNX-U 、 CORDIC-CTNX-UT 、 CrossLink-NX 、 Certus-NX 、 LIFCL-40 、 LIFCL-17 、 LFD2NX-40 、 LIFCL-40-9BG400I 、 LFD2NX-40-9BG256I |
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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October 2020 |
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Revision 1.0 |
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FPGA-IPUG-02136-1.0 |
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1.1 MB |
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