74HC138;74HCT138;3-to-8 line decoder/demultiplexer; inverting Product data sheet
The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '138 ICs and one inverter. The '138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
●Features and benefits:
■Wide supply voltage range from 2.0 to 6.0 V
■CMOS low power dissipation
■High noise immunity
■Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
■Demultiplexing capability
■Multiple input enable for easy expansion
■Ideal for memory chip select decoding
■Active LOW mutually exclusive outputs
■Input levels:
▲For 74HC138: CMOS level
▲For 74HCT138: TTL level
■Complies with JEDEC standards:
▲JESD8C (2.7 V to 3.6 V)
▲JESD7A (2.0 V to 6.0 V)
■ESD protection:
▲HBM JESD22-A114F exceeds 2000 V
▲MM JESD22-A115-A exceeds 200 V
■Multiple package options
■Specified from -40 °C to +85 °C and from -40 °C to +125 °C
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74HC138 、 74HCT138 、 74HC138D 、 74HCT138D 、 74HC138PW 、 74HCT138PW 、 74HC138BQ 、 74HCT138BQ |
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Datasheet |
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Please see the document for details |
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SO16;TSS0P16;DHVQFN16;SOT109-1;SOT403-1;SOT763-1 |
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English Chinese Chinese and English Japanese |
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13 August 2021 |
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Rev. 9 |
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74HC_HCT138 v.9 |
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269 KB |
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