Edge Detection in AT6000 FPGAs
■Edge detection is of fundamental impor-tance in image analysis. Edges charac-terize object boundaries, and are thereby very useful for registration, seg-mentation, and identification of objects in images. For example, an edge detector is commonly found in such applications as contour mapping and target recogni-tion. Similar to some digital signal pro-cessing algorithms, edge detection involves two-dimensional convolution, a compute-intensive multiply-add opera-tion. Numerous solutions such as pow-ers-of-2s [1] and vector multipliers have been proposed to alternatively manipu-late the multiply-add operation. In this paper, we will present a reference design of a fully pipelined bit-parallel edge detection circuit that, with a careful choice of convolver masks, utilizes only pipelined adders and fits into one Atmel AT6010 FPGA. We will also discuss how CacheLogic® optimizes performance of an edge detector operating on real-time video at run-time.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2021/05/19 |
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Rev. 0771A |
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109 KB |
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