MPC603e RISC Microprocessor Technical Summary
●This document is divided into two parts:
■Part I, ""MPC603e Microprocessor Overview,"" provides an overview of the MPC603e features, including a block diagram showing the major functional components.
■Part II, ""MPC603e Microprocessor Architecture Implementation,"" describes the PowerPC architecture in general, as well as providing specific details about the implementation of the MPC603e as a low-power, 32-bit member of this processor family.
●MPC603e Microprocessor Overview:
■This section describes the detailed features of the MPC603e, provides a block diagram showing the major functional units (see Figure 1), and briefly describes how these units interact. Any differences between the PID6-603e and PID7t-603e implementations are noted.
■The MPC603e is a low-power implementation of this microprocessor family of reduced instruction set computing (RISC) microprocessors. The MPC603e implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits.
■The MPC603e provides four software controllable power-saving modes. Three of the modes (the doze, nap, and sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor. The fourth is a dynamic power management mode that causes the functional units in the MPC603e to automatically enter a low-power mode when the functional units are idle without affecting operational performance, software execution, or any external hardware.
■The MPC603e is a superscalar processor that can issue and retire as many as three instructions per clock cycle. Instructions can execute out of program order for increased performance; however, the MPC603e makes completion appear sequential.
■The MPC603e integrates five execution units—an integer unit (IU), a floating-point unit (FPU), a branch processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). These execution units are (shown in Figure 1) operate independently and in parallel. The ability to execute five instructions in paralleland the use of simple instructions with rapid execution times yield high efficiency and throughput for MPC603e-based systems. Most integer instructions execute in one clock cycle. On the MPC603e, the FPU is pipelined so a single-precision multiply-add instruction can be issued and completed every clock cycle. Note that Figure 1 is a conceptual diagram and does not attempt to show how these features are physically implemented on the chip. For more information on the execution units, refer to MPC603e RISC Microprocessor User's Manual.
■The MPC603e provides address translation and protection facilities, including an ITLB, DTLB, and instruction and data BAT arrays. Instruction fetching and issuing is handled in the instruction unit.Translation of addresses for cache or external memory accesses are handled by the MMUs. Both units are discussed in more detail in Section 1.2, ""Instruction Unit,"" and Section 1.4.1, ""Memory Management Units (MMUs).""
■The MPC603e provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches for instructions and data, and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block translation. The TLBs and caches use a least recently used (LRU) replacement algorithm. The MPC603e also supports block address translation through the use of two independent instruction and data block address translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT translation takes priority.
■The MPC603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. The MPC603e interfaceprotocol allows multiple masters to compete for system resources through a central external arbiter. TheMPC603e provides a three-state coherency protocol that supports the exclusive, modified, and invalid cache states. This protocol is a compatible subset of the MESI (modified/exclusive/shared/invalid) four-state protocol and operates coherently in systems that contain four-state caches. The MPC603e supports single-beat and burst data transfers for memory accesses, and supports memory-mapped I/O operations.
■The MPC603e is fabricated using an advanced CMOS process technology and is fully compatible with TTL devices.
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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11/2001 |
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Rev. 2 |
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MPC603E/D |
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628 KB |
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