TLB Translation Setup for MPC603e and MPC755 Microprocessors
●Introduction:
■TLBs are the on-chip “caches” for page table entries for classic PowerPC memory management units (MMUs). On processors that support software table searching and on-chip TLBs, you can set up the TLBs indirectly and use them as extra BATs without the need to set up page tables in memory. The source code works exclusively on the MPC755 and MPC603e (with modifications discussed in the comments). On processors with software table searching enabled, after a TLB miss exception is taken, the interrupt handler can load a TLB entry for the offending address by executing a tlbld (or tlbli) instruction. For MPC603e and MPC755 processors, the TLB entry information that is loaded is contained in IMISS/DMISS, ICMP/DCMP, and RPA registers. This application note describes how you can load the on-chip TLBs by using these registers as conduits of information with some restrictions (see Section5, “Limitations”).
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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5/2006 |
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Rev. 1 |
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AN2795 |
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563 KB |
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