AS4C512M8D3LC 512M x 8 bit DDR3L Synchronous DRAM (SDRAM)
●Overview
■The 4Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM.
■The 4Gb chip is organized as 64Mbit x 8 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/ sec/pin for general applications.
■The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pair in a source synchronous fashion.
●Features
■JEDEC Standard Compliant
■Power supplies: V-DD & V-DDQ =+1.35V (1.283V to 1.45V)
■Backward compatible to V-DD & V-DDQ =+1.5V ±0.075V
■Operating temperature:
▲Commercial : T-C = 0~95°C
▲Industrial : T-C = -40~95°C
■Supports JEDEC clock jitter specification
■Fully synchronous operation
■Fast clock rate: 800MHz
■Differential Clock, CK & CK#
■Bidirectional differential data strobe
▲DQS & DQS#
■8 internal banks for concurrent operation
■8n-bit prefetch architecture
■Pipelined internal architecture
■Precharge & active power down
■Programmable Mode & Extended Mode registers
■Additive Latency (AL): 0, CL-1, CL-2
■Programmable Burst lengths: 4, 8
■Burst type: Sequential / Interleave
■Output Driver Impedance Control
■Average refresh period
▲8192 cycles/64ms (7.8us at -40°C ≦ T-C ≦ +85°C)
▲8192 cycles/32ms (3.9us at +85°C ≦ T-C ≦ +95°C)
■Write Leveling
■ZQ Calibration
■Dynamic ODT (Rtt_Nom & Rtt_WR)
■RoHS compliant
■Auto Refresh and Self Refresh
■78-ball 7.5 x 10.6 x 1.2mm FBGA package
▲Pb and Halogen Free
|
AS4C512M8D3LC 、 AS4C512M8D3LC-12BCN 、 AS4C512M8D3LC-12BIN 、 AS4C512M8D3LC-12BC/INXX |
|
|
512M x 8 bit DDR3L Synchronous DRAM (SDRAM) 、 Double-Data-Rate-3 (DDR3L) DRAMs 、 DRAMs |
|
|
|
|
|
Datasheet |
|
|
|
|
Please see the document for details |
|
|
|
|
|
|
|
|
FBGA |
|
|
English Chinese Chinese and English Japanese |
|
|
June.2020 |
|
|
Rev 1.0 |
|
|
|
|
|
4.5 MB |
- +1 Like
- Add to Favorites
Recommend
- Alliance Memory Bolsters Product Lineup With 4Gb High-Speed CMOS DDR4 SDRAMs AS4C256M16D4 and AS4C512M8D4
- Alliance Memory Launched High-Speed CMOS DDR3 SDRAMs With 1Gb, 2Gb, and 4Gb Densities in 78-Ball and 96-Ball FBGA Packages
- Alliance Memory Expanded Lineup of High-Speed CMOS DDR4 SDRAMs AS4C1G8D4 and AS4C512M16D4 With 8Gb Devices
- Alliance Memory AS4C256M16D4 and AS4C512M8D4 4Gb High-Speed CMOS DDR4 SDRAMs offer Low Power Consumption of +1.2V
- Alliance Memory Announces ISO 9001:2015 Recertification
- Alliance Memory AS4C1G8D4 and AS4C512M16D4: the 8Gb High-Speed CMOS DDR4 SDRAMs with Low Power Consumption of +1.2V
- Alliance Memory Expanded Lineup of DDR3 and DDR3L SDRAMs With 512Mb x8 and x16 Devices in 78-Ball and 96-Ball FBGA Packages
- Alliance Memory Announced Dual-Die 8Gb DDR3L SDRAMs AS4C1G8D3LA and AS4C512M16D3LA in 78-Ball and 96-Ball FBGA Packages
All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.
Integrated Circuits
Discrete Components
Connectors & Structural Components
Assembly UnitModules & Accessories
Power Supplies & Power Modules
Electronic Materials
Instrumentation & Test Kit
Electrical Tools & Materials
Mechatronics
Processing & Customization
