IDT71V3556 A COMPARISON OF ZERO BUS TURN-AROUND (ZBT) SRAMS AND LATE WRITE SRAMS APPLICATION NOTE
●INTRODUCTION:
■In introducing our new Zero Bus Turn-around (ZBT) SRAMs, we are frequently asked how they compare with Late Write SRAMs from other manufacturers. This application brief highlights the differences.
■Existing synchronous SRAMs are inefficient when read and write accesses are alternated. The ubiquitous pipelined burst SRAM (PBSRAM) has two idle clock cycles when a read follows a write. Best case bus efficiency is only 50% for alternating reads and writes. ZBT and Late Write both address this inefficiency but only ZBT totally eliminates idle cycles on the bus.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2020/04/05 |
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AN-204 |
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212 KB |
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