IDT71V65703 IDT71V65903 256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

2020-05-19
The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.They are designed to eliminate dead bus cycles when turning the busaround between reads and writes, or writes and reads. Thus they havebeen given the name ZBTTM, or Zero Bus Turnaround
Address and control signals are applied to the SRAM during oneclock cycle, and on the next clock cycle the associated data cycleoccurs, be it read or write.The IDT71V65703/5903 contain address, data-in and controlsignal registers. The outputs are flow-through (no output dataregister). Output enable is the only asynchronous signal and can beused to disable the outputs at any given time.A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values. There are three chip enable pins (CE1, CE2, CE2) that allow theuser to deselect the device when desired. If any one of these threeis not asserted when ADV/LD is low, no new memory operation canbe initiated. However, any pending data transfers (reads or writes)will be completed. The data bus will tri-state one cycle after the chipis deselected or a write is initiated.The IDT71V65703/5903 have an on-chip burst counter. In the burstmode, the IDT71V65703/5903 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter(ADV/LD = HIGH).The IDT71V65703/5903 SRAMs utilize a high-performance CMOS process and are packaged in a JEDEC Standard 14mm x 20mm 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and a 165fine pitch ball grid array (fBGA).

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256K x 36, 512K x 183.3V Synchronous ZBT™ SRAMs

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Commercial 、 Industrial

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100 TQFP;119 BGA;165 fBGA;BG119;BQ165

English Chinese Chinese and English Japanese

10/16/14

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