IDT71V65603/Z IDT71V65803/Z 256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs DATA SHEET
(9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one clock
cycle, and two cycles later the associated data cycle occurs, be it read or write.
The IDT71V65603/5803 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V65603/5803
to be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
The IDT71V65603/5803 have an on-chip burst counter. In the burst
mode, the IDT71V65603/5803 can provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the LBO input pin. The LBO pin selects
between linear and interleaved burst sequence. The ADV/LD signal is
used to load a new external address (ADV/LD = LOW) or increment
the internal burst counter (ADV/LD = HIGH).
The IDT71V65603/5803 SRAM utilize IDT's latest high-performance
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA) .
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IDT71V65603 、 IDT71V65803 、 IDT71V656 、 IDT71V658 、 IDT71V6560Z 、 IDT71V6580Z 、 XXXXZSXXXXXX 、 71V65803Z150PFG 、 71V65803Z150PFGI 、 71V65603Z150PFG 、 71V65603Z150PFGI 、 IDT71V65803/Z 、 IDT71V65603/Z |
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512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs 、 256K x 36 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs |
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Datasheet |
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Please see the document for details |
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Commercial 、 Industrial |
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TQFP;BGA;fBGA |
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English Chinese Chinese and English Japanese |
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OCTOBER 2008 |
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REV 02 |
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DSC-5304/08 |
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956 KB |
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