Synchronous System Halt and Run on the ADSP-CM41x Processor Engineer-to-Engineer Note
●Introduction
■The ADSP-CM41xF is a dual core mixed-signal control processor containing an Arm® Cortex®-M4 processor core and an Arm Cortex-M0 processor core. It includes several peripherals, such as the pulse-width modulators (PWM), that support motor control and inverter applications. Development on the processor is supported through the IAR Embedded Workbench and Keil™ MDK-Lite tool chains. The synchronous halt operation is used when:
▲The peripherals must s top running due to the debugger entering emulation mode (halt execution)
▲The peripherals must start running due to the debugger exiting from emulation mode (resume execution)
▲External components (such as motors) that are connected and PWMs must synchronously halt or run due to the execution or halt of the control code logic.
■Synchronous halt operation is not supported as received by debuggers like IAR and Keil. However, the ADSP-CM41xF processor is designed to support the operation in hardware. The processor uses theEmbedded Cross Trigger (ECT) which consists of the Cross Trigger Interface (CTI) and the Cross Trigger Matrix (CTM). Both the IAR Embedded Workbench C-SPY debugger and Keil debugger interface and drive the J-Link Lite emulator that supports the ADSP-CM41xF processor family. The C-SPY and μVision®support macros that can be executed when specific events occur.
■This application note provides an IAR EWARM and Keil debug scripts to set up the CTI registers to synchronously halt and run various peripherals in the system. The zip file[1]associated with this noteincludes some examples that can be executed on an ADSP-CM41xF processor evaluation board.
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ADSP-CM41x 、 ADSP-CM41xF 、 Cortex®-M4 、 Cortex M4 、 Cortex M0 、 ADSP-CM419F EZ |
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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March 21, 2019 |
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Rev 1 |
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EE-402 |
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882 KB |
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