Using VersaClock® 6 as Reference Clock for Xilinx® 7 Series FPGAs
●Introduction
■Xilinx® 7 Series FPGAs need a reference clock with relatively stringent requirements. The phase noise requirement is most notable with maximum phase noise levels at 10KHz, 100KHz and 1MHz offsets from the clock carrier frequency. This application note describes how the VersaClock 6 meets all the requirements for the Xilinx 7 Series reference clock.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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10/08/15 |
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REVISION A |
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AN-905 |
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184 KB |
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