DDR3 SDRAM Mini-UDIMM MT9JSF25672AKZ – 2GB
that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM modules
use DDR architecture to achieve high-speed operation. DDR3 architecture is essentially
an 8n-prefetch architecture with an interface designed to transfer two data words
per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module
effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal
DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O pins.
DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals.
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MT9JSF25672AK(I)Z-1G6__ 、 MT9JSF25672AK(I)Z-1G4__ 、 MT9JSF25672AK(I)Z-1G1__ 、 MT9JSF25672AKIZ-1G6 、 MT9JSF25672AKIZ-1G4 、 MT9JSF25672AKIZ-1G1 、 MT9JSF25672AKZ-1G6 、 MT9JSF25672AKZ-1G4 、 MT9JSF25672AKZ-1G1 、 MT9JSF25672AKZ-1G4K1 、 MT9JSF25672AKZ |
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Datasheet |
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Halogen-free |
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Please see the document for details |
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Commercial 、 Industrial |
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English Chinese Chinese and English Japanese |
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05/13 |
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Rev. F |
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591 KB |
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