DDR4 SDRAM VLP UDIMM MTA9ADF1G72AZ – 8GB
memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM
devices have four internal bank groups consisting of four memory banks each, providing
a total of 16 banks. 16-bit-wide DDR4 SDRAM devices have two internal bank
groups consisting of four memory banks each, providing a total of eight banks. DDR4
SDRAM modules benefit from DDR4 SDRAM's use of an 8n-prefetch architecture with
an interface designed to transfer two data words per clock cycle at the I/O pins. A single
READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bitwide,
four-clock data transfer at the internal DRAM core and eight corresponding n-bitwide,
one-half-clock-cycle data transfers at the I/O pins.
DDR4 modules use two sets of differential signals: DQS_t and DQS_c to capture data
and CK_t and CK_c to capture commands, addresses, and control signals. Differential
clocks and data strobes ensure exceptional noise immunity for these signals and provide
precise crossing points to capture input signals.
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MTA9ADF1G72AZ-3G2__ 、 MTA9ADF1G72AZ-2G6__ 、 MTA9ADF1G72AZ 、 MTA9ADF1G72AZ-3G2 、 MTA9ADF1G72AZ-2G6 、 MTA9ADF1G72AZ-3G2E1 |
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Datasheet |
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halogen-free |
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Please see the document for details |
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Commercial |
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English Chinese Chinese and English Japanese |
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11/17 |
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Rev. B |
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700 KB |
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