AS4C128M8D2A 128Mx8 DDR2 Data Sheet
access memory (SDRAM) containing 1024 Mbits in an
8-bit wide data I/Os. It is internally configured as an 8-
bank DRAM, 8 banks x 16Mb addresses x 8 I/Os.
The device is designed to comply with DDR2 DRAM
key features such as posted CAS# with additive
latency, Write latency = Read latency -1, Off-Chip
Driver (OCD) impedance adjustment and On Die
Termination(ODT).
All of the control and address inputs are synchronized
with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks
(CK rising and CK# falling). All I/Os are synchronized
with a pair of bidirectional strobes (DQS and DQS#) in
a source synchronous fashion. The address bus is used
to convey row, column, and bank address information
in RAS #, CAS# multiplexing style. Accesses begin with
the registration of a Bank Activate command, and then
it is followed by a Read or Write command. Read and
write accesses to the DDR2 SDRAM are 4 or 8-bit burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Operating the eight memory
banks in an interleaved fashion allows random access
operation to occur at a higher rate than is possible with
standard DRAMs. An auto precharge function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. A sequential
and gapless data rate is possible depending on burst
length, CAS latency, and speed grade of the device.
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AS4C128M8D2A 、 AS4C128M8D2A-25BCN 、 AS4C128M8D2A-25BIN 、 AS4C128M8D2A-25BCNTR 、 AS4C128M8D2A-25BINTR |
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Datasheet |
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Halogen Free 、 Pb Free 、 RoHS |
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Please see the document for details |
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Commercial 、 Industrial |
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FBGA |
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English Chinese Chinese and English Japanese |
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Jan. 2018 |
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Rev 1.0 |
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3.2 MB |
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