AS4C64M16D3LB-12BAN 1Gb DDR3L Data Sheet
double data rate architecture to achieve high-speed
operation. It is internally configured as an eight bank
DRAM.
The 1Gb chip is organized as 8Mbit x 16 I/Os x 8 bank
devices. These synchronous devices achieve high speed
double-data-rate transfer rates of up to 1600 Mb/sec/pin
for general applications.
The chip is designed to comply with all key DDR3L
DRAM key features and all of the control and address
inputs are synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross point
of differential clocks (CK rising and CK# falling). All I/Os
are synchronized with differential DQS pair in a source
synchronous fashion.
These devices operate with a single +1.35V-0.067V /
+0.1V power supply and are available in BGA packages.
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Datasheet |
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Halogen Free 、 Pb Free 、 RoHS |
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Please see the document for details |
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Automotive |
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AEC-Q100 |
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FBGA |
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English Chinese Chinese and English Japanese |
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Dec. 2017 |
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Rev 1.0 |
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4.4 MB |
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