IDT72V36100 3.3 VOLT HIGH-DENSITY SUPERSYNC II™36-BIT FIFO 65,536 x 36 131,072 x 36
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short.
• Asynchronous/Synchronous translation on the read or write ports
• High density offerings up to 4 Mbit
Bus-Matching Sync FIFOs are particularly appropriate for network, video,telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW), Output Width (OW), and Bus-Matching (BM) pin during the Master Reset cycle.
The input port can be selected as either a Synchronous (clocked) interface,or Asynchronous interface. During Synchronous operation the input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data present on the Dn data inputs is written into the FIFO on every rising edge of WCLK when WEN is asserted. During Asynchronous operation only the WR input is used to write data into the FIFO. Data is written on a rising edge of WR, the WEN input should be tied to its active state, (LOW).
The output port can be selected as either a Synchronous (clocked) interface,or Asynchronous interface. During Synchronous operation the output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. During Asynchronous operation only the RD input is used to read data from the FIFO. Data is read on a rising edge of RD, the REN input should be tied to its active state, LOW. When Asynchronous operation is selected on the output port the FIFO must be configured for Standard IDT mode, and the OE input used to provide three-state control of the outputs, Qn.
The frequencies of both the RCLK and the WCLK signals may vary from 0 to fMAX with complete independence. There are no restrictions on the frequency of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge,will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use.
For applications requiring more data storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use,irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any point in memory. Programmable offsets determine the flag switching threshold and can be loaded by two methods: parallel or serial. Eight default offset settings are also provided, so that PAE can be set to switch at a predefined number of locations from the empty boundary and the PAF threshold can also be set at similar predefined values from the full boundary. The default offset values are set during Master Reset by the state of the FSEL0, FSEL1, and LD pins.
For serial programming,SEN together with LD on each rising edge of WCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming, WEN together with LD on each rising edge of WCLK, are used to load the offset registers via Dn. REN together with LD on each rising edge of RCLK can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading has been selected.
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IDT72V36100 、 IDT72V36110 、 72V36100 、 72V36110 、 IDT72V36100L 、 IDT72V36110L 、 IDT72V36100L6 、 IDT72V36100L7-5 、 IDT72V36100L10 、 IDT72V36100L15 、 IDT72V36110L6 、 IDT72V36110L7-5 、 IDT72V36110L10 、 IDT72V36110L15 、 IDT72V3640 、 IDT72V3650 、 IDT72V3660 、 IDT72V3670 、 IDT72V3680 、 IDT72V36 、 72V36100L6PFG 、 72V36110L10PFGI |
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Datasheet |
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Please see the document for details |
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Commercial 、 Industrial |
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TQFP;PBGA |
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English Chinese Chinese and English Japanese |
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MARCH 2018 |
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1.1 MB |
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