ANALOG IP BLOCK LVDS_TX - CMOS LVDS Transmitter DATA SHEET
The LVDS_TX is a differential line driver designed for applications requiring high data rates. The device supports data rates up to 1Gb/s (500MHz).
The LVDS_TX accepts CMOS input levels and translates them to low voltage (350mV) differential output signals, which provides low EMI even at high frequencies.
With the companion line receiver (LVDS_RX ) it provides a new alternative to high power pseudo-ECL devices for high speed applications.
The LVDS_TX requires the cell TXBIAS for biasing. TXBIAS can drive up to 3 LVDS_TX cells. An external voltage reference must be used.
The LVDS_TX is designed as pad cell and has the same high (y-size) as austriamicrosystems AG standard pad cells with separated substrate.
●FEATURES
■LVDS_TX area: 0.184mm2, LVDS_TX size: x = 533μm y = 345.7μm
■TXBIAS area: 0.08mm2, TXBIAS size: x = 332.4μm y = 239.3μm
■3.3V ±10% supply voltage
■±350mV differential signaling
■1Gb/s maximum transmission speed
■800ps maximum propagation delay
■Power dissipation 33mW at 3.3V, static, without TXBIAS
■Junction temperature –40 - 125°C
■Compatible with IEEE 1596.3 SCI LVDS standard
■Internal 100Ω termination resistor
■High capacitive loads driving capability: 10pF @ 1Gb/s
■Power down mode
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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08.01.2004 |
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Revision D |
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594 KB |
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