CD4028BMS CMOS BCD-To-Decimal Decoder DATASHEET
decoders consisting of buffering on all 4 inputs, decoding
logic gates, and 10 output buffers. A BCD code applied to
the four inputs, A to D, results in a high level at the selected
one of 10 decimal decoded outputs. Similarly, a 3-bit binary
code applied to inputs A through C is decoded in octal code
at output 0 to 7 if D = “0”. High drive capability is provided at
all outputs to enhance dc and dynamic performance in high
fan-out applications.
The CD4028BMS is supplied in these 16-lead outline packages:
Braze Seal DIP H4S
Frit Seal DIP H1E
Ceramic Flatpack H3X
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[ Code Conversion ][ Indication-Tube Decoder ][ Address Decoding ][ Memory Selection Control ] |
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Datasheet |
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ISO9001 、 JEDEC |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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December 1992 |
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Rev 0.00 |
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FN3303 |
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595 KB |
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