CD4028BMS CMOS BCD-To-Decimal Decoder
decoders consisting of buffering on all 4 inputs, decoding
logic gates, and 10 output buffers. A BCD code applied to
the four inputs, A to D, results in a high level at the selected
one of 10 decimal decoded outputs. Similarly, a 3-bit binary
code applied to inputs A through C is decoded in octal code
at output 0 to 7 if D = "0". High drive capability is provided at
all outputs to enhance dc and dynamic performance in high
fan-out applications.
The CD4028BMS is supplied in these 16-lead outline packages:
Braze Seal DIP H4S
Frit Seal DIP H1E
Ceramic Flatpack H3X
|
[ Code Conversion ][ Indication-Tube Decoder ][ Address Decoding - Memory Selection Control ] |
|
|
Datasheet |
|
|
ISO9000 |
|
Please see the document for details |
|
|
Aerospace |
|
|
MIL-STD-883 、 QML Class V |
|
|
|
|
|
English Chinese Chinese and English Japanese |
|
|
December 1992 |
|
|
|
|
|
3303 |
|
|
215 KB |
- +1 Like
- Add to Favorites
Recommend
All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.
Integrated Circuits
Discrete Components
Connectors & Structural Components
Assembly UnitModules & Accessories
Power Supplies & Power Modules
Electronic Materials
Instrumentation & Test Kit
Electrical Tools & Materials
Mechatronics
Processing & Customization
