CD4017BMS, CD4022BMS CMOS Counter/Dividers DATASHEET
CD4022BMS - Octal Counter with 8 Decoded Outputs
CD4017BMS and CD4022BMS are 5-stage and 4-stage Johnson
counters having 10 and 8 decoded outputs, respectively.
Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal.
Schmitt trigger action in the CLOCK input circuit provides
pulse shaping that allows unlimited clock input pulse rise and fall
times.
These counters are advanced one count at the positive clock signal
transition if the CLOCK INHIBIT signal is low. Counter
advancement via the clock line is inhibited when the CLOCK
INHIBIT signal is high. A high RESET signal clears the counter to
its zero count. Use of the Johnson counter configuration permits
high speed operation, 2-input decode gating and spike-free
decoded outputs. Anti-lock gating is provided, thus assuring
proper counter sequence. The decoded output are normally low
and go high only at their respective decoded time slot. Each
decoded output remains high for one full clock cycle. A CARRYOUT
signal completes one cycle every 10 clock input cycles in
the CD4017BMS or every 8 clock input cycles in the
CD4022BMS and is used to ripple-clock the succeeding device
in a multi-device counting chain.
The CD4017BMS and CD4022BMS series types are supplied in
these 16 lead outline packages
Braze Seal DIP *H4W †H4X
Frit Seal DIP *H1F †H1E
Ceramic Flatpack H6W
*CD4017B Only † CD4022B Only
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CMOS 5-stage Counter/Dividers 、 CMOS 4-stage Counter/Dividers |
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[ Decade Counter/Decimal Decode Display (CD4017BMS) ][ Binary Counter/Decoder ][ Frequency Division ][ Counter Control/Timers ][ Divide-by-N Counting ] |
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Datasheet |
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ISO9001 、 JEDEC |
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Please see the document for details |
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DIP;Flatpack |
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English Chinese Chinese and English Japanese |
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August 1998 |
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Rev 0.00 |
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FN3297 |
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840 KB |
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