Timing Fabric for Communications Equipment
● Communication equipment requires synchronization to transport multiple services (voice, data and video) over Carrier networks. The timing fabric, as illustrated in Figure 1 and Figure 2, enables equipment such as routers, multi-service switching platforms, PON (Passive Optical Network) and DSLAM (Digital Subscriber Line Access Multiplexer), to meet the stringent synchronization requirements of communication networks.
● The architecture in Figure 1 segments the timing fabric into 2 major elements: timing cards and line cards. On the timing cards, the SETS PLLs are primarily responsible for compliance with synchronization standards. The T1/E1 LIUs receive external BITS/SSU references for the T0 DPLLs which generate standards compliant synchronous clocks and distribute them to the backplane for the line cards. Recovered clocks from the line card PHYs are used as references by the T4 DPLLs which rate convert them for the T1/E1 LIU transmitters that provide line references to the external BITS/SSU. On the line cards DPLLs select a backplane reference from one of the timing cards, the reference is rate converted and jitter attenuated to meet the needs of the specific PHYs used on these cards. Depending on the number of PHY reference clocks required on each line card a discrete fan-out buffer may also be needed. Recovered clocks from line card PHYs are rate converted to a backplane frequency (8 kHz, 19.44 MHz, or 25 MHz) and sent to the backplane for the T4 DPLLs on the timing cards.
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8T49N241 、 8T49N242 、 8T49N285 、 8T49N286 、 8T49N287 、 8V89308i 、 82P33714 、 82P33731 |
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Universal Frequency Translator 、 Jitter Attenuator 、 Multiplier |
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Technical Documentation |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2018/02/27 |
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309 KB |
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