PCI Express Reference Clock Requirements AN-843 APPLICATION NOTE
●Introduction
■This application note provides an overview of PCI Express (PCIe) reference clocking for Generations 1, 2 and 3. PCIe is a major architecture improvement over the parallel half-duplex PCI bus to a dual-simplex serial bus. This was designed to increase data throughput while minimizing the number of bus IO pins for PCs. The first generation, introduced in 2005, operated at a 2.5GBit/sec raw data rate with 8B/10B encoding for an effective data rate of 2GBit/sec. Generation 2 was introduced in 2006 and extended the raw data rate to 5Gbit/sec, also with 8B/10B encoding for an effective bit rate of 4 Gbit/sec. Generation 3 was finalized in 2010 and supports a raw bit rate of 8Gbit/Sec but using scrambling with 129B/130B encoding for an effective bit rate of 7.88Gbit/sec.
■Three PCI Special Interest Group (PCISIG) documents were used as the basis for this document. The first document is a white paper, PCI Express Jitter and BER, Revision 1.0, which provides background information regarding the following three important factors that define the link BER. The first factor, jitter, is partitioned into a random Gaussian components, Root Sum Squares (RSS) Dj and a deterministic component, Dj. These two different types of jitter are summed in accordance with the Double Delta function method. Second, a bit error is defined “... as the accumulation of phase jitter, y, such that the total phase differencebetween the data and the sampling clock exceeds ½ the unit interval (UI).” Third is a simple link phase noise model to define the random and deterministic components of the jitter budget.
■The link phase noise model is developed to define the random and deterministic components of the jitter budget and a procedure to measure the jitter of a specific link. Compliance of a particular RefClock with the PCIe jitter specifications has been further developed from this initial white paper and is determined indirectly through a three-step process. First a phase transfer function model for the particular clock architecture is defined. Second the phase noise at the model output is calculated when driven by a particular RefClock oscillator phase noise spectrum. Third the model output jitter spectrum is processed for comparison to the PCIe high and low band specs. For rms jitter the phase noise is integrated over the appropriate frequency bands. For peak-to-peak jitter the filtered clock spectrum must be transformed back into the time domain to find the two specific instants at which the eye closure function deviates to the positive and negative phase extremes.
■The second document is the CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0, which provides the Gen 1 reference clock architectures, modeling parameters and requirements. Third is the PCI Express BASE SPECIFICATION, REV. 3.0, which contains the reference clock architectures, modeling parameters and requirements for Gen 2 and Gen 3.
■This note is concerned only with the jitter requirements for the Reference Clock partition of the jitter budget and its associated jitter transfer model. PCISIG has made an effort to maintain the phase noise performance requirements on the Reference Clock oscillator as each new PCIe generation has been introduced. The objective is to minimize the design effort necessary to guarantee jitter compliant Reference Clock designs, which places the bulk of the low noise design burden on the PCIe transmitters and receivers.
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PCI Express reference clocking 、 PCIe reference clocking 、 Reference Clock |
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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05/12/14 |
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REVISION A |
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AN-843 |
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2.2 MB |
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