Ultra Series™ Crystal Oscillator Si561 Data Sheet
DSPLL® technology to provide an ultra-low jitter, low phase noise clock at
two selectable frequencies. The device is factory-programmed to provide any two
selectable frequencies from 0.2 to 3000 MHz with <1 ppb resolution and maintains
exceptionally low jitter for both integer and fractional frequencies across its operating
range. The Si561 offers excellent reliability and frequency stability as well as
guaranteed aging performance. On-chip power supply filtering provides industryleading
power supply noise rejection, simplifying the task of generating low jitter
clocks in noisy systems that use switched-mode power supplies. Offered in industry-standard
3.2x5 mm and 5x7 mm footprints, the Si561 has a dramatically simplified
supply chain that enables Silicon Labs to ship custom frequency samples 1-2
weeks after receipt of order. Unlike a traditional XO, where a different crystal is required
for each output frequency, the Si561 uses one simple crystal and a DSPLL
IC-based approach to provide the desired output frequencies. This process also
guarantees 100% electrical testing of every device. The Si561 is factory-configurable
for a wide variety of user specifications, including frequency, output format,
and OE pin location/polarity. Specific configurations are factory-programmed at
time of shipment, eliminating the long lead times associated with custom oscillators.
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[ 100G/200G/400G OTN, coherent optics ][ 10G/25G/40G/100G Ethernet ][ 3G-SDI/12G-SDI/24G-SDI broadcast video ][ Servers, switches, storage, NICs, search acceleration ][ Test and measurement ][ Clock and data recovery ][ FPGA/ASIC clocking ] |
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Datasheet |
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ESD(HBM,2000V) 、 IPC-7351 、 MIL-STD-883 、 RoHS |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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June, 2018 |
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Rev. 1.0 |
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1.3 MB |
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