Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide
●About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP
■The Low Latency E-Tile 40G Ethernet (LL E-Tile 40GbE) Intel® FPGA IP is used in multiple variants of the Stratix® 10 and Agilex™ 7device families. The IP core implements the IEEE 802.3-2010 40G Ethernet Standard and includes options to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard.
■The MAC client side interface for the Low Latency E-Tile 40G Ethernet Intel FPGA IP is a 128-bit Avalon® streaming interface and a 32-bit Avalon memory-mapped interface control path. The network interfaces are standard XLAUI interfaces.
■The IP provides standard media access control (MAC), physical coding sublayer (PCS), and physical medium attachment (PMA) functions.
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2024.04.09 |
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559 KB |
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