Low Latency 40-Gbps Ethernet Intel® FPGA IP User Guide: Stratix® 10

PublishTime：2024-07-29

●About the Low Latency 40G Ethernet Core

■The Stratix® 10 Low Latency 40-Gbps Ethernet IP core implements the IEEE 802.3-2010 40G Ethernet Standard. The IP core includes options to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard and to support the IEEE 802.3-2012 Backplane Ethernet Standard.

■The MAC client side interface for the Stratix 10 Low Latency 40G Ethernet IP core is a 128-bit Avalon® streaming interface (Avalon-ST).

■The IP core provides standard media access control (MAC), physical coding sublayer (PCS), and physical medium attachment (PMA) functions. The PHY comprises the PCS and PMA.

Brand of Product：	INTEL
Part#：	Stratix® 10 、 Stratix 10 More Part#
Product Category：	FPGA More
Application：	More
Data Type：	User's Guide More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	2024.05.31
Version Number：
Data Encoding：
Data Size：	810 KB

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