MM32F5270 MM32F5280 32-bit Microcontrollers based on Arm China STAR-MC1 User Manual
■The MM32F5270 and MM32F5280 microcontroller is based on ARM®STAR-MC1 processor. Built-in L1 ICache, DCache, instruction tightly coupled memory ITCM and data tightly coupled memory DTCM, with high performance and low power consumption.
■The main system consists of 32-bit multilayer AHB (Mullti-AHB) bus matrix that interconnects:
▲Up to six bus masters
◆CBUS(Code AHB Bus)
◆SBUS(System AHB Bus)
◆DMA1
◆DMA2
◆USB_FS DMA
◆ENET DMA
▲Up to eight bus slaves
◆Internal eFlash memory
◆Internal SRAM1 (112KB)
◆Internal SRAM2 (16KB)
◆TBUS (TCM Slave bus)
◆AHB1 peripherals
◆AHB2 peripherals
◆FSMC
◆QSPI
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2023/01/12 |
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Version: 0.9 |
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59.5 MB |
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