AS4C512M8D3A-12BAN Revision History 4Gb AS4C512M8D3A-12BAN-78ball FBGA PACKAGE
rate architecture to achieve high-speed operation. It is
internally configured as an eight bank DRAM.
The 4Gb chip is organized as 64Mbit x 8 I/Os x 8 bank
devices. These synchronous devices achieve high
speed double-data-rate transfer rates of up to 1866
Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3
DRAM key features and all of the control and address
inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the
cross point of differential clocks (CK rising and CK#
falling). All I/Os are synchronized with differential DQS
pair in a source synchronous fashion.
These devices operate with a single 1.5V ± 0.075V
power supply and are available in BGA packages.
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Datasheet |
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Halogen Free 、 JEDEC 、 Pb Free 、 RoHS |
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Please see the document for details |
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Automotive |
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AEC-Q100 |
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English Chinese Chinese and English Japanese |
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May 2016 |
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Rev. 1.0 |
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4.6 MB |
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