Renesas RA Family Guidelines for Using the S Cache on the System Bus
●Caches can effectively improve instruction or data access speed for microcontroller and microprocessor systems with mismatch between CPU and slower SRAM. Even though there are no internal caches in the Cortex-M23 and Cortex-M33 processors, for some Renesas RA Family Cortex-M33 MCUs, there are system level caches for both instruction cache and data cache present, which help to improve instruction and data fetch speed.
●The cache enabling and configuration for the instruction cache are handled by the Renesas Flexible Software Package (FSP). The cache enabling, disabling, and flushing functionality for the data cache are demonstrated in this application project with reference software projects provided. In addition, this application project provides guidelines and example code for keeping the data cache coherent. Use this application project as a reference resource for S Cache operations.
●The data cache is named S Cache in the Renesas RA Family Cortex-M33 MCU Hardware User’s Manual. The S Cache is on the MCU’s system bus. The instruction cache is named C Cache and is on the code bus. This application note is focused on the data cache usage of the RA MCUs. For consistency, this application note uses S Cache throughout the rest of the application note. At the time of the release of this application project, the RA Family MCU groups that support the S Cache are RA6M5, RA6M4, RA6E1, and RA4M3. User can review the MCU Hardware User’s Manual Buses section and look for the Cache section to understand whether the any new MCUs include S Cache and its general operations.
●For other RA6 Series MCUs which do not have S Cache, they are provided with SRAMHS. Access to the SRAMHS is always no wait state. Use the SRAMHS on these MCUs when improved SRAM access is needed.
●The example project provided is based on EK-RA6M5. You can easily port the example project to other MCUs which support S Cache. The performance improvement of using S Cache on an MCU varies based on the MCUs memory access speed, memory size, the nature of the SRAM access pattern of the application code, You need to analyze all these aspects when evaluating the S Cache.
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Cortex-M33 MCUs 、 Cortex-M23 and Cortex-M33 processors 、 Evaluation Kit 、 MCU |
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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Jan.06.22 |
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Rev.1.00 |
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R11AN0538EU0100 |
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1.5 MB |
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