ISLA118P50 8-Bit, 500MSPS A/D Converter
■The device utilizes two time-interleaved 250MSPS unit A/Ds to achieve the ultimate sample rate of 500MSPS. A single 500MHz conversion clock is presented to the converter, and all interleave clocking is managed internally. The proprietary Interleave Engine (I2E) performs automatic fine correction of offset, gain, and sample time skew mismatches between the unit A/Ds to optimize performance. No external interleaving algorithm is required.
■A serial peripheral interface (SPI) port allows for extensive configurability of the A/D. The SPI also controls the interleave correction circuitry, allowing the system to issue continuous calibration commands as well as configure many dynamic parameters.
■Digital output data is presented in selectable LVDS or CMOS formats. The ISLA118P50 is available in a 72-contact QFN package with an exposed paddle. Performance is specified over the full industrial temperature range (-40°C to +85°C).
■Features
●1.15GHz Analog Input Bandwidth
●90fs Clock Jitter
●Automatic Fine Interleave Correction Calibration
●Multiple Chip Time Alignment Support via the Synchronous Clock Divider Reset
●Programmable Gain, Offset and Skew Control
●Over-Range Indicator
●Clock Phase Selection
●Nap and Sleep Modes
●Two’s Complement, Gray Code or Binary Data Format
●DDR LVDS-Compatible or LVCMOS Outputs
●Programmable Test Patterns and Internal Temperature Sensor
8-Bit, 500MSPS A/D Converter 、 low-power, high-performance, 500MSPS analog-to-digital converter |
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[ Radar ][ Electronic ][ Signal Intelligence ][ Broadband Communications ][ High-Performance Data Acquisition ] |
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Datasheet |
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Please see the document for details |
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QFN |
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English Chinese Chinese and English Japanese |
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Jul 6, 2021 |
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Rev.3.0 |
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FN7565 |
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2.6 MB |
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