8A34001 Synchronization Management Unit
■The 8A34001 Synchronization Management Unit (SMU) provides tools to manage timing references, clock sources, and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators, Digitally Controlled Oscillators (DCO), or Digital Phase Lock Loops (DPLL).
■Optional clock recovery filter/servo software is available under license from Renesas for use with the 8A34001. The filter/servo software is designed to suppress the effects of Packet Delay Variation (PDV) on packet based timing signals – it can be used with protocol stacks for IEEE 1588 or other packet-based timing protocols.
8A34001 、 8A3xxxx Family 、 8A3xxxx 、 8A34001E-dddAJG 、 8A34001E-dddAJG8 |
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[ Core and access IP switches ][ routers ][ Synchronous Ethernet equipment ][ Telecom Boundary Clocks ][ T-BCs ][ Telecom Time Slave Clocks ][ T-TSCs ][ 10Gb Ethernet interfaces ][ 40Gb Ethernet interfaces ][ 100Gb Ethernet interfaces ][ Central Office Timing Source ][ 4.5G network equipment ][ 5G network equipment ] |
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Datasheet |
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Please see the document for details |
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144-CABGA |
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English Chinese Chinese and English Japanese |
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November 25, 2021 |
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4.9 MB |
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