Cyclone III Development Board Reference Manual
■This document describes the hardware features of the Cyclone®III development board, including detailed pinout information to enable designers to create custom FPGA designs that interface with all components of the board.
●General Description:
■The Cyclone®III development board provides a hardware platform for developing and prototyping low-power, high-volume, feature-rich designs as well as to demonstrate the Cyclone III device’s on-chip memory, embedded multipliers, and the Nios®II embedded soft processor.
■With up to 4-Mbits of embedded memory and 288 embedded 18-bit x 18-bit multipliers, the Cyclone III device supplies an abundance of internal memory while also providing external support for high-speed, low-latency memory access via dual-channel DDR SDRAM and low-power SRAM.
■Built on TSMC’s 65-nm low-power process technology, Cyclone III devices are designed to provide low static and dynamic power consumption. Additionally, with the support of the Quartus®II software’s PowerPlay technology, designs are automatically optimized for power consumption. Therefore, the Cyclone III development board provides a power-optimized, integrated solution for memory-intensive, high-volume applications.
■Accordingly, the Cyclone III development board is especially suitable for wireless, video and image processing, and other high-bandwidth, parallel processing applications. Through the use of Altera®-provided video and image intellectual property (or other MegaCore® functions) and board expansion connectors, you can enable the inter-operability of the Cyclone III device, allowing application-specific customization of the development board.
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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March 2008 |
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Version 1.1.0 |
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1.5 MB |
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