1Gb (128Mx8) DDR3L AS4C128M8D3LC 78ball FBGA PACKAGE
●The 1Gb Double-Data-Rate-3L (DDR3L) DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM.
●The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications.
●The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pair in a source synchronous fashion.
■Features:
●JEDEC Standard Compliant
●Power supplies: V-DD & V-DDQ =+1.35V (1.283V ~ 1.45V)
●Backward compatible to V-DD & V-DDQ =+1.5V ±0.075V
●Operating temperature:
●Supports JEDEC clock jitter specification
●Fully synchronous operation
●Fast clock rate: 800MHz
●Differential Clock, CK & CK#
●Bidirectional differential data strobe
◆DQS & DQS#
●8 internal banks for concurrent operation
●8n-bit prefetch architecture
●Pipelined internal architecture
●Precharge & active power down
●Programmable Mode & Extended Mode registers
●Additive Latency (AL): 0, CL-1, CL-2
●Programmable Burst lengths: 4, 8
●Burst type: Sequential / Interleave
●Output Driver Impedance Control
●Auto Refresh and Self Refresh
●Average refresh period
◆8192 cycles/64ms (7.8us at -40°C ≦ T-C ≦ +85°C)
◆8192 cycles/32ms (3.9us at +85°C ≦ T-C ≦ +95°C)
●Write Leveling
●ZQ Calibration
●Dynamic ODT (Rtt_Nom & Rtt_WR)
●RoHS compliant
●78-ball 7.5 x 10.5 x 1.0mm FBGA package
◆Pb and Halogen Free
1Gb (128Mx8) DDR3L 、 DDR3L Synchronous DRAM (SDRAM) 、 1Gb Double-Data-Rate-3L (DDR3L) DRAMs |
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Datasheet |
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Please see the document for details |
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78ball FBGA;78-ball FBGA |
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English Chinese Chinese and English Japanese |
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June. 2022 |
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Rev 1.0 |
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6.1 MB |
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