AS4C128M8D3LB-12BIN AS4C128M8D3LB-12BCN 1Gb DDR3L Data Sheet
double data rate architecture to achieve high-speed
operation. It is internally configured as an eight bank
DRAM.
The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 bank
devices. These synchronous devices achieve high speed
double-data-rate transfer rates of up to 1600 Mb/sec/pin
for general applications.
The chip is designed to comply with all key DDR3L
DRAM key features and all of the control and address
inputs are synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross point
of differential clocks (CK rising and CK# falling). All I/Os
are synchronized with differential DQS pair in a source
synchronous fashion.
These devices operate with a single +1.35V-0.067V /
+0.1V power supply and are available in BGA packages.
|
AS4C128M8D3LB-12BIN 、 AS4C128M8D3LB-12BCN 、 AS4C128M8D3LB 、 AS4C128M8D3LB-12BINTR 、 AS4C128M8D3LB-12BCNTR |
|
|
|
|
|
Datasheet |
|
|
Halogen Free 、 Pb Free 、 RoHS |
|
Please see the document for details |
|
|
Commercial 、 Industrial |
|
|
|
|
|
FBGA |
|
|
English Chinese Chinese and English Japanese |
|
|
Jan. 2018 |
|
|
Rev 1.0 |
|
|
|
|
|
4.5 MB |
- +1 Like
- Add to Favorites
Recommend
All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.
Integrated Circuits
Discrete Components
Connectors & Structural Components
Assembly UnitModules & Accessories
Power Supplies & Power Modules
Electronic Materials
Instrumentation & Test Kit
Electrical Tools & Materials
Mechatronics
Processing & Customization
