EFM8BB3x Revision B
●Description of Change:
Silicon Labs is pleased to announce revision B of the EFM8BB3x devices, revision 0.3 of the corresponding datasheet, revision 0.3 of the corresponding Reference Manual, revision 0.4 of the corresponding errata, and revision 0.1 of the corresponding errata history for these products.
Revision B Changes:
Crystal Mode in External Oscillator is available in revision B
In revision A, crystal mode in the external oscillator option is not available. It is available in revision B.
VREF/P0.0 output can be retained in revision B:
VREF/P0.0 output on revision A devices is not retained if the PINRETAIN bit in PCON1 is set (in addition to the RSTMD bit in the DAC) and drops from its level to 0 V on any non-POR reset. This problem has been fixed in revision B.
Timer 3/4 chaining mode in suspend works in all system clock divider settings in revision B:
The Timer 3/4 32-bit counter on revision A devices does not switch to the low frequency oscillator (LFOSC0) after entering suspend mode if the system clock divider is set to a value of divide-by-4 or greater. This problem has been fixed in revision B. Timer 3/4 chaining mode in suspend mode works in all system clock divider values.
CLU wake-up sources are edge triggered in revision B:
CLU interrupt-enabled Suspend or Snooze wake-up sources are level triggered on revision A devices. On revision B devices these wake sources are edge triggered as described in device reference manual.
I2CSLAVE0 can distinguish between multiple addresses in revision B:
I2CSLAVE0 can respond to multiple slave addresses and distinguish between these addresses using the receive FIFO when the ADDRCHK bit in I2C0CN0 is set to 1 in revision B. The ADDRCHK bit is not available on revision A devices.
REVID SFR will read 0x01 in revision B:
The reset value of REVID SFR will read 0x01 in revision B instead of 0x00 in revision A
Revision 0.3 Data Sheet Changes
Debug section:
Added figure 5.2 in section 5.2 to describe the debug connections that are required.
UART bootloader information:
Added information about the UART bootloader in Section 3.10 Bootloader
Bootloader User Guide reference:
Added a reference to AN945: EFM8 Factory Bootloader User Guide in Section 3.10 Bootloader
Pre-programmed UART bootloader:
Added pre-programmed UART bootloader in Section 1 Feature List
Revision B part numbers:
Updated all orderable part numbers to revision B part numbers in Table 2.1 Product Selection Guide
(note: added one part number that was not in Rev A EFM8BB31F16G-B-QFN24)
Crystal mode in external oscillator:
Specified external crystal/RC oscillator feature in Section 1 Feature List and Section 3.4 Clocking
QFN32 PCB land pattern:
Adjusted C1, C2 X2, Y2, and Y1 maximum dimensions in Section 7.2 QFN32 PCB Land Pattern
QFN32 and QSOP24 package markings:
Adjusted package markings for QFN32 package in Section 7.3 QFN32 Package Marking and QSOP24 package in Section 10.3 QSOP24 Package Marking
DAC differential nonlinearity min/max:
Changed DAC differential nonlinearity minimum from TBD to -1 and maximum from TBD to 1 in Table 4.12 DACs
Revision 0.4 Errata Changes:
Revision 0.3 errata #1 XOSC_E101 – Crystal Mode in External Oscillator Not Available has been removed in revision 0.6 errata. The problem has been corrected in revision B of the device.
Revision 0.3 errata #2 RST_E101 – VREF/P0.0 Not Retained through Power-On Reset has been removed in revision 0.4 errata. The problem has been corrected in revision B of the device.
Revision 0.3 errata #3 TIMER_E101 – Timer 3/4 Chaining Mode in Suspend has been removed in revision 0.4 errata. The problem has been corrected in revision B of the device.
Revision 0.3 errata #4 CLU_E101 – CLU Wake-Up Sources are Level Triggered has been removed in revision 0.4 errata. The problem has been corrected in revision B of the device.
Revision 0.3 errata #5 I2CSLAVE_E101 – I2CSLAVE0 Cannot Distinguish Between Multiple Addresses has been removed in revision 0.4 errata. The problem has been corrected in revision B of the device.
Revision 0.3 errata #6 PKG_E101 – Top Marking Right Justified has been removed in revision 0.4 errata. The package marking issue only affects revision A QFP32 devices with a date code of 1531.No revision B devices have been affected.
Revision 0.3 errata #7 PKG_E102 – Devices Marked as G Grade has been removed in revision 0.4 errata. The package marking issue only affects revision A QFP32 devices with a date code of 1540 or 1602. No revision B devices have been affected.
Revision 0.3 errata #8 TEST_E101 – Devices Tested to 85 °C has been removed in revision 0.4 errata. This issue only affects revision A devices with a date codes of 1530, 1531, or 1532. No revision B devices have been affected.
After the effective date of this PCN, Silicon Labs reserves the right to deliver revision B for customersordering revision A.
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