AD3200xxE-x 2Gb LPDDR3 datasheet

2022-05-13
●Features
■DLL is not implemented
■Low power consumption
■JEDEC LPDDR3-compliance
■Partial Array Self-Refresh (PASR)
■Auto Temperature Compensated Self-Refresh (ATCSR) by built-in temperature sensor
■Deep power-down mode
■Double-data-rate architecture; two data transfers per one clock cycle
■The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
■Differential clock inputs (CK_t and CK_c)
■Commands entered on each positive CK_t edge; data and data mask referenced to both edges of DQS
■Data mask (DM) for write data

AP Memory

AD3200xxE-xAD320032EAD320016EAD320032E-XAD320016E-XAD320032E-ABAD320016E-ABAD325616D-XT-AB

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LPDDR3 RAM

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Datasheet

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Please see the document for details

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BGA134;134B;FBGA

English Chinese Chinese and English Japanese

Sep. 07, 2021

Rev. 1.1a

2.2 MB

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