AD3200xxE-x 2Gb LPDDR3 datasheet
■DLL is not implemented
■Low power consumption
■JEDEC LPDDR3-compliance
■Partial Array Self-Refresh (PASR)
■Auto Temperature Compensated Self-Refresh (ATCSR) by built-in temperature sensor
■Deep power-down mode
■Double-data-rate architecture; two data transfers per one clock cycle
■The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
■Differential clock inputs (CK_t and CK_c)
■Commands entered on each positive CK_t edge; data and data mask referenced to both edges of DQS
■Data mask (DM) for write data
AD3200xxE-x 、 AD320032E 、 AD320016E 、 AD320032E-X 、 AD320016E-X 、 AD320032E-AB 、 AD320016E-AB 、 AD325616D-XT-AB |
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Datasheet |
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Please see the document for details |
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BGA134;134B;FBGA |
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English Chinese Chinese and English Japanese |
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Sep. 07, 2021 |
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Rev. 1.1a |
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2.2 MB |
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