LA-ispMACH 4000V/Z® Automotive Family

PublishTime：2022-07-25

●Introduction:
■The high performance LA-ispMACH 4000V/Z automotive family from Lattice offers a SuperFAST CPLD solution that is tested and qualified to the AEC-Q100 standard. The family is a blend of Lattice’s two most popular architectures: the ispLSI® 2000 and ispMACH 4A. Retaining the best of both families, the LA-ispMACH 4000V/Z architecture focuses on significant innovations to combine the highest performance with low power in a flexible CPLD family.
■The LA-ispMACH 4000V/Z automotive family combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictability, routing, pinout retention and density migration.
■The LA-ispMACH 4000V/Z automotive family offers densities ranging from 32 to 128 macrocells. There are multiple density-I/O combinations in Thin Quad Flat Pack (TQFP) packages ranging from 44 to 144 pins. Table 2.1 and Table 2.2 show the macrocell, package and I/O options, along with other key parameters.
■The LA-ispMACH 4000V/Z automotive family has enhanced system integration capabilities. It supports 3.3 V (4000V and 1.8 V (4000Z) supply voltages and 3.3 V, 2.5 V and 1.8 V interface voltages. Additionally, inputs can be safely driven up to 5.5 V when an I/O bank is configured for 3.3 V operation, making this family 5 V tolerant. The LA-ispMACH 4000V/Z also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The LA-ispMACH 4000V/Z automotive family is in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK, TMS, TDI and TDO are referenced to VCC (logic core).
●Overview:
■The LA-ispMACH 4000V/Z automotive devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 3.1.
■The I/Os in the LA-ispMACH 4000V/Z automotive devices are split into two banks. Each bank has a separate I/O power supply. Inputs can support a variety of standards independent of the chip or bank power supply. Outputs support the standards compatible with the power supply provided to the bank. Support for a variety of standards helps designers implement designs in mixed voltage environments. In addition, 5 V tolerant inputs are specified within an I/O bank that is connected to VCCO of 3.0 V to 3.6 V for LVCMOS 3.3, LVTTL and PCI interfaces.

Brand of Product：	Lattice
Part#：	LA-ispMACH 4000V/Z 、 IEEE 1149.1 、 IEEE 15 、 LA-ispMACH 4032V 、 LA-ispMACH 4032V/Z 、 LA-ispMACH 4064V/Z 、 LA-ispMACH 4128V More Part#
Product Category：	SuperFAST CPLD More
Application：	More
Data Type：	Datasheet More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	September 2017
Version Number：	Version 2.6
Data Encoding：	FPGA-DS-02021-2.6
Data Size：	2.7 MB

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