74LVC1G08 Single 2-input AND gate Product data sheet
The 74LVC1G08 is a single 2-input AND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall time.
This device is fully specified for partial power-down applications using I-OFF. The I-OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
●Features and benefits
■Wide supply voltage range from 1.65 V to 5.5 V
■High noise immunity
■±24 mA output drive (V-CC = 3.0 V)
■CMOS low power dissipation
■Direct interface with TTL levels
■Overvoltage tolerant inputs to 5.5 V
■I-OFF circuitry provides partial Power-down mode operation
■Latch-up performance ≤ 250 mA
■Complies with JEDEC standard:
▲JESD8-7 (1.65 V to 1.95 V)
▲JESD8-5 (2.3 V to 2.7 V)
▲JESD8C (2.7 V to 3.6 V)
▲JESD36 (4.5 V to 5.5 V)
■ESD protection:
▲HBM JESD22-A114F exceeds 2000 V
▲MM JESD22-A115-A exceeds 200 V
■Multiple package options
■Specified from −40 °C to +85 °C and −40 °C to +125 °C
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74LVC1G08 、 74LVC1G08GW 、 74LVC1G08GV 、 74LVC1G08GF 、 74LVC1G08GN 、 74LVC1G08GS 、 74LVC1G08GX 、 74LVC1G08GM |
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Datasheet |
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Please see the document for details |
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TSSOP5;SC-74A;XSON6;X2SON5;SOT353-1;SOT753;SOT886;SOT891;SOT1115;SOT1202;SOT1226-3;MO-203;SC-88A;MO-252 |
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English Chinese Chinese and English Japanese |
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24 February 2022 |
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Rev. 14 |
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74LVC1G08 v.14 |
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648 KB |
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