18-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
●General description
■The 74ALVC162834A is an 18-bit registered driver. Data flow is controlled by active low output enable (OE), active LOW latch enable (LE), and clock input (CP).
■WhenLE is LOW, the A to Y data flow is transparent. WhenLE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP, the A data is stored in the latch/flip-flop.
■The 74ALVC162834A is designed with 30 Ω series resistors in both HIGH or LOW output stages.
■When OE is LOW, the outputs are active. WhenOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latch/flip-flop.
■To ensure the high-impedance state during power-up or power-down,OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
●Features and benefits
■Wide supply voltage range from 1.2 V to 3.6 V
■CMOS low-power consumption
■Direct interface with TTL levels(2.7 V to 3.6 V)
■Current drive ±12 mA at 3.0 V
■MULTIBYTE flow-through standard pin-out architecture
■Low inductance multiple Vcc and GND pins for minimum noise and ground bounce
■Output drive capability 50 Ω transmission lines at 85º C
■Integrated 30 Ω termination resistors
■Diode clamps to Vcc and GND on all inputs
■Input diodes to accommodate strong drivers
■Complies with JEDEC standard no.8-1A
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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13 June 2017 |
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Rev. 3 |
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426 KB |
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