USB3DevIP Data Recorder by FAT32 Design
■The demo system implements USB3 Device IP to be USB3 Mass storage device by using DDR3 RAM on the board to be data storage. The design is specially designed for 24hrs-run data recording system through USB3 interface. To compatible with standard system, record data is stored in FAT32 file system, so PC can design test application by using standard open/read file to dump the record data. In the demo, “recv_fat32_rec.exe” test application is designed to dump record data with/without data verification.
■The hardware system is designed by using CycloneVE/ArriaV GX development board which has 512/256 MB DDR3 RAM to be storage. USB3 interface is implemented by using USB3HSMC adapter board to connect FPGA board to PC in device mode.
■The demo uses 256/512 MB DDR3 RAM available on FPGA board to be record data storage. Special firmware is implemented on CPU within FPGA to emulate DDR3 RAM to be 32 GB storage size with FAT32 file system. When plugged-in the system to PC, PC will detect 32 GB storage with 947 available files in FAT32 system. 947 files consists of 945 record data files (F0000.BIN – F0944.BIN), and two control files (REC_STS.BIN, READ_STS.BIN). The feature of each file is follows.
▲The record data file size is fixed to be 32 MB. Each file valid status is monitored through REC_STS.BIN.
▲REC_STS.BIN is 4-byte size to show the latest file number which record data is valid. Maximum valid file depends on DDR3 size (7 files for 256 MB and 15 files for 512 MB). Valid value of the latest file number is 0-944 and default value after system boot-up or stop recording is 0xFFFF_FFFF. For example, if value is 200, it means that F0186.BIN/F0194.BIN – F0200.BIN are valid. This file is updated by CPU on FPGA board, and PC can read only.
▲READ_STS.BIN is 4-byte size to show the latest file number which PC has been read. Similar to REC_STS.BIN, valid value is 0-944 and default value after system boot-up or stop recording is 0xFFFF_FFFF. This file is updated by PC and FPGA board will read this file to flush the record data from DDR3. For example, if value is 200, it means that F0186.BIN/F0194.BIN – F0200.BIN have been already read. CPU on FPGA board can flush these data from DDR3 and replace new data to DDR3.
■To read control files which are 4-byte size, test application on PC (“rec_fat32_rec.exe”) is implemented with special setting to avoid read cache. It needs to use direct access to see the updated value from the hardware in REC_STS.BIN. For record data, total file size (32 MBx945) is bigger than cache size, so the test application can read the updated record data without special setting. Test application must read data in a sequence starting from F0000.BIN to F0945.BIN, and then restart to read F0000.BIN to dump the data continuously.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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13-Mar-15 |
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Rev 1.1 |
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682 KB |
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