FPGA Setup for TOE/UDP1G IP with CPU Demo

PublishTime：2022-03-31

●This document describes how to setup FPGA board and prepare the test environment for running TOE1G-IP or UDP1G-IP demo. The user can setup two test environments for transferring TCP data or UDP data via 1Gb Ethernet connection by using TOE1G-IP or UDP1G-IP, as shown in Figure 1-1.
●First uses one FPGA board and Test PC with 1Gb Ethernet card for transferring the data. TestPC runs test application, i.e.,tcpdatatest (half-duplex test for TOE1G-IP),tcp_client_txrx_40G for (full-duplex test for TOE1G-IP)or udp1gdatatest (test application for UDP1G-IP).Also, Serial console is run on Test PCto be user interface console.
●Second uses two FPGA boards which may be different board or the same board. Both boards run TOE1G-IP or UDP1G-IP demo with assigning the different initialization mode (Client for Server) for transferring data.

Brand of Product：	Design Gateway
Part#：	ZC706 、 KC705 、 AC701 、 TOE1G-IP 、 UDP1G-IP More Part#
Product Category：	FPGA development boards More
Application：	More
Data Type：	User's Guide More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	10-Nov-20
Version Number：	Rev 3.0
Data Encoding：
Data Size：	2.8 MB

Data section preview(2pages)

- The full preview is over. If you want to read the whole 13 page document,please Sign in/Register -

Download

+1 Like
Add to Favorites

Recommend

Technical Resources

More>

All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.

Integrated Circuits